The present application is related to concurrently filed non-provisional applications:
(i) by A. W. Hietala entitled Fractional-N Modulation with Analog IQ Interface;
(ii) by S. R. Humphreys and B. T. Hunt entitled Dual-Modulus Prescaler;
(iii) by A. W. Hietala and S. R. Humphreys entitled Fractional-N Synthesizer with Improved Noise Performance; and
(iv) by A. W. Hietala and S. R. Humphreys entitled Accumulator with Programmable Full-Scale Range, which non-provisional applications are assigned to the assignee of the present invention, and are hereby incorporated in the present application as if set forth in their entirety herein.
The present invention relates to digital logic circuits. More particularly, the present invention relates to dynamic flip-flop circuits. Still more particularly, the present invention relates to true single-phase dynamic flip-flop circuits.
The class of logic circuits known as dynamic logic circuits has gained considerable favor in recent years by offering advantages in many applications in speed and power dissipation when compared with many prior circuit techniques. See, for example, J. M. Rabaey, Digital Integrated Circuits, Prentice-Hall, 1996, especially pp. 222-234 and 347-363. Early dynamic flip-flops employed a two-phase clock controlling operations in precharge and evaluation modes of operation.
More recently, a variety of so-called true single-phase clock (TSPC) dynamic circuits have provided increased flexibility in designs while maintaining speed and power advantages. See, J. Yuan and C. Svensson, xe2x80x9cNew Single-Clock CMOS Latches and Flipflops with Improved Speed and Power Savings,xe2x80x9d IEEE J Solid-State Circuits, vol. 32, pp. 62-69, January, 1997, and Rabaey, supra, at pp. 359-363.
FIG. 1 shows a prior art TSPC-1 full-latch flip-flop (sometimes, TSPC1FL, but hereinafter TSPC-1 flip-flop) of a type described generally in the above-cited paper by Yuan and Svensson. This circuit operates as a negative edge-triggered flip-flop that is advantageously viewed as comprising three CMOS stages: an input stage (from input D to node A), a middle stage (from node A to node B), and an output stage (from node B to output /Q). In FIG. 1, the MPi, i=1-4 are PMOS devices and the MNj,j=1-6 are NMOS devices.
Table 1 illustrates operation of the respective stages of the circuit of FIG. 1 during high and low clock phases.
In Table 1, tristate refers to a high impedance state that effectively disconnects devices MP4 and MN5 from output lead /Q, (as well as MP2 and MN3 from node B) in accordance with standard industry usage.
FIG. 2 shows waveforms appearing over time at identified locations in the circuit of FIG. 1 in relation to an input clock signal (CLK). The output at /Q is updated at each high-to-low transition of CLK, at which time the output stage changes from a tristate holding state to operation as a CMOS inverter in accordance with Table 1. The circuit of FIG. 1 avoids one glitch that occurs due to charge sharing when an input at node D remains low for more than one cycle of CLK. See further, Q. Huang and R. Rogenmoser, xe2x80x9cSpeed Optimization of Edge-Triggered CMOS Circuits for Gigahertz Single-Phase Clocks,xe2x80x9d IEEE J Solid-State Circuits, vol. 31, pp. 456-465, March 1996.
However, the TSPC-1 flip-flop of FIG. 1 exhibits another glitch in high frequency operation across process and environmental variations that arises from a different mechanism than that identified by Huang et al., cited above. To illustrate this latter glitch it proves useful to consider the following example. Assume the clock signal is high and the D input signal is at a logic high. Also assume that the output (/Q) is currently holding a low logic level during its tristate mode. Under these conditions the input stage has discharged so that node A is a logic low and the middle stage is performing the function of an inverter so that node B is a logic high. The output stage is in the tristate mode with the output holding a logic low signal from the previous low phase of the input clock.
Since the D input is at a logic high, when the clock transitions from high to low, the /Q output value should remain at a logic low as the output stage transitions from tristate operation to inverter operation. However, the /Q output signal will exhibit a glitch where the output logic low value spikes high on the high-to-low transition of CLK before returning to the correct logic low value after the clock settles low. This is shown in the /Q waveform of FIG. 2 at reference numeral 3. Across temperature and process variations, the magnitude of this glitch is large enough to improperly trigger following logic stages.
It has previously been found that proper operation of TSPC-1 flip-flops can be improved by judiciously choosing sizes of critical transistors to reduce glitches. Unfortunately, most transistors in TSPC-1 flip-flops have conflicting sizing requirements; roles played by individual transistors change, e.g., from drivers to loads, and vice versa, with clock phase changes. Thus, for a given clock phase, a particular transistor may function as a driver (indicating that it should have a relatively large size). In contrast, the same transistor may switch roles and function as a load (indicating that the it should have a relatively small size) on the next phase of the clock. Therefore, sizing of transistors in a TSPC-1 flip-flop to achieve maximum operating frequency is a balance between two conflicting sizing requirements, as noted in the above-cited paper by Huang and Rogenmoser.
Particular sizing of transistors in a TSPC-1 flip-flop for high frequency operation may introduce glitches like the one demonstrated above, but resizing to reduce glitches can reduce the maximum operating frequency of these flip-flops. Furthermore, sizing compromises generally result in increases in the overall size of the flip-flop, thereby reducing its maximum operating frequency. In addition, if it is possible to remove the dual (driver/load) nature of a critical transistor, the size of the transistor can be optimized for maximum operating frequency, but often at the expense of increased circuit complexity and/or power dissipation.
Accordingly, a need exists to improve the circuit of FIG. 1 to remove glitches of the type shown in FIG. 2. Moreover, such needed improvements desirably avoid any substantial increase in power consumption, undue circuit complexity, or reduced maximum operating frequency while removing such glitches. A particular need exists for such improved operation for application to circuits such as the dual-modulus synchronous divider sections of a dual-modulus prescaler of the types described in incorporated patent application (ii) cited above.
Limitations of the prior are overcome and a technical advance is made in accordance with the present invention, typical embodiments of which are described below.
In particular, illustrative embodiments of improved TSPC-1 flip-flop circuits are described that are based, in part, on the observation that the logic level stored on node B of the circuit of FIG. 1 during the high phase of the clock is the inverse of the future logic value to be transferred to the /Q output on the subsequent high to low transition of the clock. It therefore proves advantageous to invert this logic level and transfer it directly to node C, preserving the current value of the /Q output. This approach exploits the off state of MP4 occurring during the high clock phase, while pre-setting the logic level at node C to the correct future /Q output value. This method also allows any charge that might be previously stored on node C, to discharge to VSS during the high clock phase. In this manner, the momentary connection of the /Q output to node C does not cause a glitch in the output-since the final value of the output has already been pre-set on node C.
In accordance with one illustrative embodiment of the present invention the TSPC-1FL flip-flop of FIG. 1 is modified by the addition of corrective circuitry applied to node C. Corrective circuitry in the illustrative embodiment comprises two NMOS transistors added to the TSPC-1 flip-flop of FIG. 1 that are only active during the high clock phase (while the output stage exhibits tristate operation), thereby avoiding interference with operation of the output stage in its inverter mode.
Other illustrative embodiments also include a NAND input logic arrangement and additional output circuitry to provide complementary output signals.
These and other embodiments of the present invention may be realized in circuit designs that avoid transistor size increases in selected transistors as suggested in prior work. Embodiments based on present inventive teachings therefore remove the undesired glitches without reducing maximum operating frequency and without substantial increase of power consumption.